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ICs for TV
AN5095K
Single chip IC with I2C bus interface for PAL/NTSC color TV system
s Overview
The AN5095K is an IC in which PAL/NTSC color television signal processing circuits are integrated into a single chip. Also, since the I2C bus interface is built in the IC, the rationalization of set production line can be realized.
58.40.3 64 33 17.00.2
Unit: mm
* Built- in video IF circuit, sound IF circuit, video signal processing circuit, color signal processing circuit, sync. signal processing circuit * Suitable for PAL/NTSC/AV-NTSC/M-NTSC systems * 6 dB improved sound S/N (compared with the AN5195K-B/-C) * Package: 64-SDIP, supply voltage: 5 V, 9 V
(3.3) 0.7 min. 5.2 max.
3.850.2
s Features
1
32
(1.641) Seating plane
1.778
(1.0)
0.5+0.1 -0.05
19.05 0.25+0.1 -0.05
0 to 15
SDIP064-P-0750B
s Applications
* Television and televideo
1
ICs for TV
SIF regulator filter Video out Sync. in V-OSC APC1 Y-in 45 44 43 42
*7-bit VCO CV clamp Sharpness phase shift *6-bit Y contrast Black expansion Y clamp
SECAM interface
58
51
41
63
64
62
61
60
59
57
56
55
54
53
52
50
49
48
47
46
40
39
38
37
36
35
Saturation *6-bit Ver. out H-VCO H-BLK AFC1 SCP Ver. count down R-Y demod. Matrix +/- 50 Hz/60 Hz detect BGP *2-bit (50 Hz/ 60 Hz) B-Y demod. *3-bit AFC2 Her. count down PN/S SW Shut down Hor. reg. *1-bit G-Y
Hor. sync. sep.
APC1
Ver. sync. sep. Hor. lock det.
*9-bit AFT
Video SW *1-bit
SIF SW *2-bit
LImiter
Killer ident
R, G, B SW
HVBLK
LPF System SW *1-bit 1H FF
SIF detect
Tint
LPF
B-clamp
CW generate
G-clamp
*6-bit APC
ACC amp.
*3-bit
Deemphasis
Level adjust
R-clamp 2-bit Brightness Killer, *7-bit 50 Hz/60 Hz SECAM det. SW
*1-bit
1-bit
VIF detect Chroma VCO ACC det.
(*6-bit)
IF AGC R G B * Drive 7-bit * Drive 7-bit * Cutoff 8-bit * Cutoff 8-bit * Cutoff 8-bit Contrast
DAC out SW out
Pre-amp.
34
VCO
*6-bit
I2C bus interface
23 14 24 12 16 18 19 11 13 15 17 20 10 21 22
IF amp.
RF AGC
*1-bit
26
25
28
29
31
27
s Block Diagram
Killer out 50 Hz/60 Hz out SECAM det. out
VCC3 (VIF/SIF)
VCC1 (9 V)
VIF1 in
30
4
5
6
9
G-clamp filter
R-clamp filter
B-clamp filter
De-emphasis
Hor. lock det.
Ext. video in
Killer
Ys-in
G-in
R-in
B-in
ACL
SDA
SCL
APC
4.43 MHz
G-out
R-out
B-out
3.58 MHz
RF AGC
BL det.
VIF2 in
Audio out
AFT
AN5095K
GND (R, G, B/DAC)
GND (VIF/SIF)
De-coupling
32
1
2
3
7
8
33
ASW
SIF3 in/sharpness
GND (V, C, J)
VCC3 (V, C, J)
X-ray protect
Int. Video2
Int. Video1
Ver. clamp
-(R-Y) out
-(B-Y) out
-(R-Y) in
-(B-Y) in
SIF APC
Det. out
IF AGC
H-OSC
SIF1 in
SIF2 in
FBP in
VOUT
AFC1
AFC2 VCC2
H-out
SCP
C-in
2
ICs for TV
s Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (R) clamp (G) clamp (B) clamp Killer filter Killer out, 50 Hz/60 Hz out, SECAM det. out Chroma APC filter Chroma VCO (4.43 MHz) Chroma VCO (3.58 MHz) Black level det./Blank off SW YS input (fast blanking) External R-input External G-input External B-input VCC1 R-output G-output B-output Hor.lock detect GND (R, G, ACL SDA SCL VCC3-1 (VIF/SIF) VIF1 input VIF2 input GND (VIF/SIF) RF AGC output Audio output De-emphasis AFT output External video input DC De-coupling filter B/I2C/DAC) Description Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Description SIF3 input/sharpness SIF regurator filter SIF2 input SIF1 input IF AGC filter Internal videol input SIF APC filter Internal video2 input VIF detect output VIF APC 1 filter VIF VCO (fP/2) Video output Y-input H, V sync. input
AN5095K
VCC3-2 (chroma/jungle/DAC) Chroma input/black expansion start GND (video/chroma/jungle) FBP input VCC2 (hor. stability supply) AFC2 filter AFC1 filter Hor. VCO (32 fH) X-ray protection input Hor. pulse output Ver. sync. clamp Ver. pulse output SECAM interface -(B-Y) output -(R-Y) output Sandcastle pulse output -(B-Y) input -(R-Y) input
3
AN5095K
s Absolute Maximum Ratings
Parameter Supply voltage VCC Symbol VCC1 (14) VCC3 (23, 47) Supply current ICC I14 I23+47 I51 Power dissipation *2 Operating ambient temperature *1 Storage temperature
*1
ICs for TV
Rating 10.5 6.0 67 126 27 1 480 -20 to +70 -55 to +150
Unit V
mA
PD Topr Tstg
mW C C
Note) *1: Except for the operating ambient temperature, and storage temperature, all ratings are for Ta = 25C. *2: The power dissipation shown is for the IC package in free air at Ta = 70C.
s Recommended Operating Range
Parameter Supply voltage Symbol VCC1 VCC3 Terminal voltage V5 V10 V11 V12 V13 V21 V22 V27 V30 V48 V50 V55 V59 Supply current Circuit current I51 I15 I16 I17 I41 I44 I46 4 Range 8.1 to 9.9 4.5 to 5.5 0 to 6 0 to 6 0 to 6 0 to 6 0 to 6 0 to 6 0 to 6 0 to 10.5 0 to 10.5 0 to V14 0 to V47 0 to 2 0 to V14 10 to 25 -3.2 to +0.6 -3.2 to +0.6 -3.2 to +0.6 - 0.8 to +0.8 -1.1 to +0.4 - 0.8 to +0.1 mA mA V Unit V
ICs for TV
s Recommended Operating Range (continued)
Parameter Circuit current Symbol I56 I58 I59 Range -6.4 to +0.1 - 0.8 to +0.1 - 0.3 to +0.1
AN5095K
Unit mA
Note) Do not apply external currents or voltages to any pins not specifically mentioned. For circuit currents, '+' denotes current flowing into the IC, and '-' denotes current flowing out of the IC.
s Electrical Characteristics at Ta = 25C
Parameter Power Supply Supply current 1 Supply current 2 Supply current 3 Stabilized supply voltage Stabilized supply current Stabilized supply input resistance VIF circuit I14 I23 I47 V51 I51 R51 Current at V14 = 9 V Current at V23 = 5 V Current at V47 = 5 V Voltage at I51 = 15 mA Current at V51 = 5 V DC measurement, slant between at I51 = 10 mA and 25 mA Modulation m = 87.5%, data 0B = 44 39 7 49 5.8 2 1 48 10 63 6.5 5 5 57 13 77 7.2 7 10 mA mA mA V mA Symbol Conditions Min Typ Max Unit
Typical input; fP = 38.9 MHz, VIN = 90 dB, DAC data are typical VPO 1.7 1.9 1.1 5.5 1.6 1.0 75 -1.2 2.1 2.6 1.6 8 2.0 2.0 -2.0 0 2.5 3.3 2.1 12 2.4 -1.0 95 1.2 V[p-p] V[p-p] V[p-p] MHz V MHz MHz dB MHz VPOmax 0B = 74 VPOmin 0B = 04 fPC VSP fPPH fPPL Frequency which becomes -3 dB for 1 MHz output Synchronized peak value voltage at V[p-0] measurement High-pass side pull-in range (difference from fP = 38.9 MHz) Low-pass side pull-in range (difference from fP = 38.9 MHz)
Video detection output (typ.) Video detection output (max.) Video detection output (min.) Video detection outputfrequency characteristic Synchronous peak value voltage APC high-level pull-in range APC low-level pull-in range RF AGC delay point adjustable range *1 VCO free-running frequency
VRFDP Delay point in which data are 0A = 00 to 3F (input at V27 = approx. 6.5 V) fP Dispersion without VIN V37 (IF AGC) = 0 V (measurement of the difference from 38.9 MHz) Max. current IC can sink when pin 27 is low IC leak current at which pin 27 is high
RF AGC maximum sink current RF AGC minimum sink current
IRFmax IRFmin
1.5 - 50
3.0 0
50
mA A
Note) *1 to *9: Refer to "Explanation of test methods".
5
AN5095K
s Electrical Characteristics at Ta = 25C (continued)
Parameter VIF circuit (continued) AFT discrimination sensitivity *2 AFT center voltage AFT maximum output voltage AFT minimum output voltage Detection output resistance SIF circuit Symbol AFT VAFT Conditions f = 25 kHz V30 at VIN without input Min Typ
ICs for TV
Max
Unit
Typical input; fP = 38.9 MHz, VIN = 90 dB, DAC data are typical 40 4.0 7.8 0.3 70 57 4.5 8.1 0.8 120 75 5.0 8.7 1.0 170 mV/kHz V V V
VAFTmax V30 at f = fP -500 kHz VAFTmin V30 at f = fP +500 kHz RO41 DC measurement, IO = - 0.4 V to -1.0 mA
Typical input; fS = 6.0 MHz, fM = 400 Hz, VIN = 90 dB VSOP36 f = 50 kHz 0B-D3 = 0 VSOP35 f = 50 kHz 0B-D3 = 0 VSOP33 f = 50 kHz 0B-D3 = 0 RSN/P VSOP fSNH (4.5M) fSNL (4.5M) fSPH (5.5M) fSPL (5.5M) fSPH (6.0M) fSPL (6.0M) fSPH (6.5M) fSPL (6.5M) R29P R29N f = 25 kHz 0B-D3 = 1, ratio to PAL (VSOP36) fS = 5.5 MHz and 6.0 MHz ratio to 6.5 MHz Pull-in range of high-pass side Pull-in range of low-pass side Pull-in range of high-pass side Pull-in range of low-pass side Pull-in range of high-pass side Pull-in range of low-pass side Pull-in range of high-pass side Pull-in range of low-pass side Impedance of pin 29 at PAL Impedance of pin 29 at NTSC 0.90 0.90 0.90 -2.5 -3 4.8 5.8 6.3 6.8 32 48 1.15 1.15 1.15 - 0.5 0 5.0 4.0 6.0 5.0 6.5 5.5 7.0 6.0 40 60 1.40 1.40 1.40 1.5 3 4.2 5.2 5.7 6.2 48 72 V[rms] V[rms] V[rms] dB dB MHz MHz MHz MHz MHz MHz MHz MHz k k
Audio detection output (PAL, SIF1) Audio detection output (PAL, SIF2) Audio detection output (PAL, SIF3) Audio detection output NTSC/PAL Audio detection output linearity SIF pull-in range NTSC (4.5 MHz) SIF pull-in range NTSC (4.5 MHz) SIF pull-in range PAL (5.5 MHz) SIF pull-in range PAL (5.5 MHz) SIF pull-in range PAL (6.0 MHz) SIF pull-in range PAL (6.0 MHz) SIF pull-in range PAL (6.5 MHz) SIF pull-in range PAL (6.5 MHz) De-emphasis terminal output resistance (PAL) De-emphasis terminal output resistance (NTSC)
Note) *1 to *9: Refer to "Explanation of test methods".
6
ICs for TV
s Electrical Characteristics at Ta = 25C (continued)
Parameter AV SW circuit Video SW voltage gain Video SW-frequency characteristic Video SW external input terminal voltage Video SW external output DC voltage Video SW external input resistance Video SW output resistance GVSW fVSW V31 V44E RI31 RO44 f = 1 MHz, VIN = 1 V[p-p] Frequency to become -3 dB from f = 1 MHz, VIN = 0.714 V[0-p] DC measurement DC measurement, 03-D7 = 1, 0B-D7 = 1 DC measurement DC measurement, IO = - 0.6 mA to -1.0 mA DC measurement, IIN = -1.0 mA DC measurement Data 03-D7 = 1, 0B-D7 = 1, (input from outside) f = 400 Hz, VIN = 1 V[p-p] DC measurement DC measurement Data 03 = 20 (typ.) (contrast) 5.7 8 1.7 4.2 44 110 1.4 3.7 -1 6.7 10 2.0 4.8 56 150 1.7 4.3 0 Symbol Conditions Min Typ
AN5095K
Max
Unit
7.7 2.3 5.4 68 190 2.0 4.9 1
dB MHz V V k V V dB
Video SW internal clamp terminal V38, 40 voltage Video SW internal output DC voltage Audio SW voltage gain V44I GASW
Audio SW output DC voltage Audio SW output resistance Video signal processing circuit Video output (typ.) Video output (max.) Video output (min.) Contrast variable range Video frequency characteristic Picture quality variable range Pedestal level (typ.) Pedestal variable width Brightness control sensitivity Video input clamp voltage ACL sensitivity Blanking level
V28 RO28
3.7 350
4.2 450
4.7 550
V
Typical input; 0.6 V[p-p] (VBW = 0.42 V[p-p] stair-step) at G-out VYO 2.0 4.1 0.15 15 5.5 9 2.0 2.5 5.0 0.50 20 6.0 13 2.5 2.75 20 3.7 3.2 1.0 3.0 5.9 1.00 25 17 3.0 3.35 26 4.2 3.7 1.5 V[0-p] V[0-p] V[0-p] dB MHz dB V V mV/Step V V/V V VYOmax Data 03 = 3F (max.) VYOmin Data 03 = 00 (min.)
YCmax/min 03 = 3F 03 = 00 fYC Pin 33 = 5 V (sharpness), frequency to become -3 dB from f = 0.2 MHz f = 3.8 MHz
YSmax/min V33 = 7V V33 = 5V VPED VPED VBRT VYCLP ACL VYBL
Data 02 = 40 (typ.) (brightness)
Difference between data 02 = 00 and 7F 2.15 Average amount of change per 1-step between data 02 = 30 and 50 Pin 45 clamp voltage Amount of change of Y-out, when V20 = 3.0 V 3.5 V Blanking pulse DC voltage 14 3.2 2.7
7
AN5095K
s Electrical Characteristics at Ta = 25C (continued)
Parameter Symbol Conditions Min 90 Typ 100
ICs for TV
Max
Unit
Video signal processing circuit (continued) Service SW threshold voltage DC restoration ratio
*
Typical input; 0.6 V[p-p] (VBW = 0.42 V[p-p] stair-step) at G-out 0.3 110 V %
VSTH TDC
Voltage at which vertical output stops when pin 20 (ACL) voltage is decreased APL10% to 90% AC - DC TDC = x 100 AC DC measurement; Sink current inside of IC
Video input clamp current Pedestal difference voltage Brightness voltage tracking Video voltage gain relative ratio Video voltage gain tracking Color signal processing circuit Color-difference output (typ.) Color-difference output (max.) Color-difference output (min.) Contrast adjustable range ACC characteristic 1 ACC characteristic 2 NTSC tint center NTSC tint adjustable range 1 NTSC tint adjustable range 2 Color-difference output ratio (R) Color-difference output ratio (G) Color-difference output angle (R) Color-difference output angle (G) PAL color killer tolerance NTSC color killer tolerance APC high-lebel pull-in range APC low-lebel pull-in range Color killer detection output voltage (color)
IYCLP VIPL TBL GYC
6
11 0 1.0 1.0 1.0
16 0.2 1.1 1.2 1.1
A V Time Time Time/ Time
Pedestal difference voltage of R, G, B-out - 0.2 Ratio of R, G, B-out fluctuation level for data 02 (bright) = 20 to 60 Output ratio of R, B-out against G-out 0.9 0.8 0.9
TCONT Ratio of gain of R, G, B-out for data 03 (contrast) = 10 to 30 Burst 150 mV[p-p] (PAL), reference is B-out VCO Input; Color bar Data 00 = 20 (typ.), 03 = 20 (typ.)
2.9 2.6 15 0.9 0.8 -7 30 - 65 0.46 0.28 78 224 - 57 - 57 450 4.5
3.7 3.3 20 1.0 1.0 0 50 - 50 0.56 0.34 90 236 - 44 - 44 700
4.5 100 25 1.2 1.2 7 65 - 30 0.66 0.40 102 248 - 34 - 34
V[p-p] V[0-p] mV[p-p] dB Time Time Step deg deg Time Time deg deg dB dB Hz Hz V
VCOmax Data 03 = 3F, amplitude of one side 03 = 20 VCOmin Data 00 = 00, 03 = 20 CCmax/min 03 = 3F 03 = 00 ACC1 ACC2 C 1 2 R/B G/B R G VKILLP 00 = 20
Burst 150 mV[p-p] 300 mV[p-p] Burst 150 mV[p-p] 30 mV[p-p] The difference from data 01 = 20 at which tint is adjusted to center Input; Rainbow data 01 = 3F Input; Rainbow data 01 = 00 Input; Rainbow for both PAL/NTSC Input; Rainbow for both PAL/NTSC Input; Rainbow for both PAL/NTSC Input; Rainbow for both PAL/NTSC 0 dB = 150 mV[p-p]
VKILLN 0 dB = 150 mV[p-p] fCPH fCPL VKC Both PAL/NTSC Both PAL/NTSC V5 , killer out at which chroma input data 0A-D6 = 0, 0A-D7 =1
-700 - 450 5.0
Note) *: Since pin 20 is also used partly as service SW when used as ACL, a sufficient care must be taken so as not to become V20 < 0.9 V in carrying out set design.
8
ICs for TV
s Electrical Characteristics at Ta = 25C (continued)
Parameter Symbol Conditions Min Typ
AN5095K
Max
Unit
Color signal processing circuit (continued) Color killer detection output voltage (B & W) Demodulation output -(B-Y) Demodulation output -(R-Y) Demodulation output angle (B-Y) Demodulation output angle (R-Y) CW output level (4.43 MHz)
*3
Burst 150 mV[p-p] (PAL), reference is B-out 0 555 430 -6 84 250 1.31 50 4.5 0.8 4.1 0.1 695 540 0 90 350 1.41 100 5.0 1.3 4.6 0.5 835 650 6 96 450 50 1.51 150 1.65 5.1 V mV[p-p] mV[p-p] deg deg mV[p-p] mV[p-p] ms A V V V
VKBW VDB VDR RDB RDR VCWP VCWN tCW ISECAM VSE V59PN V59S GDV
V5 , killer out at which chroma input data 0A-D6 = 0, 0A-D7 =1 Input; Color bar measured at pin 60 for both PAL/NTSC Input; Color bar measured at pin 61 for both PAL/NTSC B-Y axis out of phase B-Y axis phase difference AC component, when VCO is set at 4.43 MHz AC component, when VCO is set at 3.58 MHz Period in which CW is outputted at SECAM, PAL The minimum value to take out current from pin 59 to discriminate as SECAM V5 , det. out, when SECAM signal input data 0A-D6 = 1, 0A-D7 = 0, SECAM V59 DC level at PAL/NTSC V59 DC level at SECAM AC change amount for R, B-out between drive adjustment max. and min.
CW output level (3.58 MHz) *3 CW output level period (SECAM) *3 SECAM judgment current SECAM judgment output PAL/NTSC DC level SECAM DC level RGB processing circuit Drive adjusting range Offset adjusting range YS threshold voltage YS threshold voltage External R, G, B pedestal difference voltage Internal and external pedestal difference voltage External R, G, B output voltage
DAC data are typicals 5 2.2 1.0 - 200 - 200 1.8 0.8 12 6 2.5 0 0 2.2 1.0 17 7 2.8 0.4 200 200 2.7 1.2 22 dB V V V mV mV V[p-p] Time dB
VCUT-OFF DC change amount for R, G, B-out between offset adjustment max. and min. VYSON VYSOF VEPL Minimum DC voltage at which YS turns on Maximum DC voltage at which YS turns off YS = 1 V is applied
VPL/IE Internal part external part VERGB Input 0.7 V[p-p], contrast 03 = 20 (typ.)
External R, G, B output difference VERGB Input 0.7 V[p-p], contrast 03 = 20 (typ.) voltage External R, G, B contrast variable ECmax/min 03 = 3F range 03 = 00
Note) *1 to *9: Refer to "Explanation of test methods".
9
AN5095K
s Electrical Characteristics at Ta = 25C (continued)
Parameter Symbol Conditions Min Typ
ICs for TV
Max 1.06
Unit
RGB processing circuit (continued) External R, G, B frequency characteristic Internal and external R, G, B output voltage ratio fRGBC VE/I
DAC data are typicals Input 0.2 V[p-p] External part 0.7 V[p-p]/internal part 0.6 V[p-p] input, contrast 03 = 20 (typ.) 8 0.78 10 0.92 MHz Time
Synchronizing signal processing circuit Horizontal free run frequency Horizontal output pulse duty cycle Horizontal pull-in range PAL horizontal free run frequency NTSC vertical free run frequency Vertical output pulse width PAL vertical pull-in range NTSC vertical pull-in range Horizontal high-level output voltage Horizontal low-level output voltage Vertical high-level output voltage Vertical low-level output voltage Screen center variable range fHO HO fHP fVO-P fVO-N VO fVPP fVPN V56H V56L V58H V58L THC Without sync. signal input Upward pulse duty cycle Difference from fH = 15.625 kHz Data 01-D7 = 1, 02-D7 = 0, forced 50 Hz mode, without sync. signal input Data 01-D7 = 1, 02-D7 = 1, forced 60 Hz mode, without sync. signal input For both PAL/NTSC fH = 15.625 kHz, forced 50 Hz mode fH = 15.75 kHz, forced 60 Hz mode High-level DC voltage Low-level DC voltage High-level DC voltage Low-level DC voltage Change amount of phase difference between sync. and H-out of data 0B = 40 to 47 15.33 15.63 15.93 31 37 43 52 62 11 54 64 3.4 0.3 4.5 0.3 4.4 0.76 55 63 1.7 5.0 500 650 48 58 9 46 56 2.8 3.9 2.6 0.60 47 57 1.1 3.4 50 60 10 3.1 4.2 3.2 0.68 1.4 4.2 kHz % Hz Hz Hz 1/fH Hz Hz V V V V s V Hz Hz V V
Overvoltage protection operation VX-RAY The pin 55 minimum voltage at which voltage H-out does not appear any longer Vertical frequency discrimination (50) Vertical frequency discrimination (60) Synchronous signal clamp voltage Horizontal output start voltage f50 f60 V46 VfHS Vertical frequency at which V5 becomes low (< 0.5 V) Vertical frequency at which V5 becomes high (> 4.5 V) V46 clamp voltage The minimum V50 at f0 > 10 kHz and horizontal oscillation output is higher than 1 V[p-p]
I2C interface Sink current when ACK SCL, SDA signal high level input SCL, SDA signal low level input Allowable maximum input frequency IACK VIHI VILO fImax The maximum value of pin 21 sink current at ACK 1.5 3.1 2.0 5.0 0.9 100 mA V V kbit/s
10
ICs for TV
s Electrical Characteristics at Ta = 25C (continued)
* Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
AN5095K
Parameter VIF circuit
Symbol
Conditions Input level at which VPO1 becomes -3 dB Input level at which VPO1 becomes +1 dB
Min 50 0.5 46 1 0.1 90 2.0 3
Typ
Max 5 5 3.0 200 4 0.3 15 10 110 3.5 5 5
Unit
Typical input; fP = 38.9 MHz, VIN = 90 dB VPS VPmax SNP DGP DPP
*4
Input sensitivity Maximum allowable input SN ratio Differential gain Differential phase Black-noise detection level Black-noise clamp level
*4
45 110 - 45 45 1.2 4.0 300 300
dB dB dB % deg IRE IRE dB kHz dB V/step V/step % % k pF dB kHz/mV MHz dB kHz kHz
VBN GRF fPD IM SRF SAFT
Difference from sync. peak value Input level difference, when V27 = 1 V goes to 7 V Frequency drift from 5 sec. to 5 min. after SW-on VfC - VfP = -2 dB, VfS - VfP = -12 dB Output voltage in data 1-step, average change amount of V27 Output voltage in data 1-step, average change amount of V30 VCC = 10% Ta = -20C to +70C f = 38.9 MHz f = 38.9 MHz fS = 38.9 MHz - 6.0 MHz, P/S = 20 dB V42 = 0.1 V Free-running frequency change width at data 0C = 00 to 7F
VBNC Difference from sync. peak value
RF-AGC operation sensitivity VCO switch-on drift Inter modulation *5 RF-AGC adjustment sensitivity AFT offset adjustment sensitivity
Video detection output fluctuation VP/V with VCC Video detection outputtemperature characteristics Input resistance (pin 24, pin 25) Input capacitance (pin 24, pin 25) Sound-IF output level VCO control sensitivity VCO adjustment range RF-AGC delay point-temperature characteristics VCO free-running frequencytemperature characteristics VP/T RI24,25 CI24,25 VSIF P fVCO
VDP/T Ta = -20C to +70C fP/T Ta = -20C to +70C
AFT center frequency-temperature fAFT/T Input frequency at which AFT output characteristics voltage becomes 4.5 V, Ta = -20C to +70C External mode output DC voltage V41EXT Output DC voltage at AV-SW outside mode
Note) *1 to *9: Refer to "Explanation of test methods".
0.5
1.0
1.8
V
11
AN5095K
s Electrical Characteristics at Ta = 25C (continued)
* Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
ICs for TV
Parameter SIF circuit
Symbol
Conditions Input level, when VSOP becomes -3 dB AM = 30% f = 50 kHz f = 50 kHz, fM = 400 Hz, on/off VCC = 10% Ta = -20C to +70C DC measurement DC measurement f = 1 MHz, VIN = 1 V[p-p], inside inside f = 1 MHz, VIN = 1 V[p-p], inside outside, outside inside fS = 6.5 MHz, fM = 400 Hz, VIN = 1 V[p-p], fS = 6.5 MHz, fM = 1.0 kHz, VIN = 1 V[p-p]
Min 55 55
Typ 31.5 31.5
Max
Unit
Typical input; fS = 6.0 MHz, fM = 400 Hz, VIN = 90 dB VLIM AMR THD SNA VS/V VS/T RI35 RI36 CTVII CTVEI CTAII 50 1.0 10 10 - 55 - 55 - 60 dB dB % dB % % k k
Input limiting level AM rejection ratio Total harmonic distortion SN ratio Audio output fluctuation with VCC Audio output - temperature characteristics SIF input resistance SIF input resistance AV-SW circuit Video-SW crosstalk (inside inside) Video-SW crosstalk (outside inside) Audio-SW crosstalk (inside inside) Video signal processing circuit Black level expansion 1
*6
dB dB dB
Typical input; 0.6 V[p-p] (VBW = 0.42 V[p-p] stair-step) at G-out VBL1 VBL2 VBL3 Input: All black, difference between pin 9 = 9 V and open (with RC) Input: All black, difference between pin 9 = 3 V and 9 V Input: Approx. 20 IRE, voltage difference between pin 9 = open and 9 V at 03 (contrast) = 3F (max.) Y-out output difference at sharpness between max. and min. -100 400 100 0 700 300 100 1000 500 mV mV mV
Black level expansion 2 *
6
Black level expansion 3 *6
Contrast change by sharpness Brightness change by sharpness Input dynamic change Y-signal SN-ratio Black level expansion start point *6 Video output fluctuation with VCC Video output - temperature characteristics ACL start point
VCS VBS VImax SNY VBLS VY/V VY/T VACL
- 300
0 0 42 3.7
300 250 1.6 47 15 10 4.0
mV mV V[p-p] dB IRE % % V
Pedestal level DC difference at sharpness - 250 between max. and min. 03 (contrast) = 20 (typ.) 03 (contrast) = 3F (max.) Start point at V48 = 4.5 V VCC1 = 9 V (allowance: 10%) Ta = -20C to +70C V20 at which the output amplitude becomes 90% when ACL terminal (V20) is decreased from 5 V 53 37 3.4
Note) *1 to *9: Refer to "Explanation of test methods".
12
ICs for TV
s Electrical Characteristics at Ta = 25C (continued)
* Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
AN5095K
Parameter Color signal processing circuit Demodulation output residual carrier Color-difference output residual carrier VCO free-running frequency (PAL) VCO free-running frequency (NTSC) fCO fluctuation with VCC Static phase error (PAL) Static phase error (NTSC) PAL/NTSC ratio Line crawling Color-difference output bandwidth Color-difference output fluctuation with VCC Color-difference output temperature characteristics PAL/NTSC output impedance SECAM output impedance Color, black & white DC difference voltage (C-Y)/Y ratio *7 RGB processing circuit YS change-over speed Outside R, G, B input dynamic range Inside and outside crosstalk
Symbol
Conditions
Min -300 -300 -300 0.7 1.0 400 100 - 60 0.9
Typ 1.0 510 0 1.2
Max
Unit
Burst 150 mV[p-p] (PAL), reference is B-out VCAR1 VCAR2 fCP fCN 2fSC level of pin 60 and pin 61 2fSC level of pin 15, pin 16 and pin 17 Difference from f = 4.433619 MHz Difference from f = 3.579545 MHz 30 50 300 300 300 5 5 1.3 50 15 15 620 60 1.5 mV mV Hz Hz Hz deg/ 100 Hz deg/ 100 Hz Time mV MHz % % k mV V[0-p]/ V[0-p]
fC /VCC VCC1 = 9 V (allowance: 10%), VCC3 = 5 V (allowance: 10%) P N RP/N VPAL fCC VC/V VC/T Tint gap at fC = -300 Hz to +300 Hz change Tint gap at fC = -300 Hz to +300 Hz change Output amplitude ratio between PAL and NTSC Pin 61: Output amplitude difference per 1H at -(R-Y) terminal Band to become -3 dB VCC1 = 9 V (allowance: 10%), VCC3 = 5 V (allowance: 10%) Ta = -20C to 70C
RO60,61PN DC measurement RO60,61S DC measurement VCBW Pedestal voltage difference between with and without burst signal RC/Y Color bar input, B-out contrast typ. color data 00 = 30
fYS VDEXT CTRGB
fYS , when YS input is 3 V[0-p] and output level is -3 dB Contrast max. data 03 = 3F Leakage at f = 1 MHz, 1 V[p-p], YS = 5 V
7 1.0

-50
MHz V[p-p] dB
Synchronizing signal processing circuit Lock detection output voltage Lock detection charge and discharge current VLD ILD V18 at horizontal AFC lock DC measurement 5.7 0.6 6.3 0.8 6.9 1.1 V mA
Note) *1 to *9: Refer to "Explanation of test methods".
13
AN5095K
s Electrical Characteristics at Ta = 25C (continued)
* Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
ICs for TV
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Synchronizing signal processing circuit (continued) FBR (R, G, B) slice level FBP (AFC2) slice level Horizontal AFC Horizontal VCO Burst gate pulse position
*8
VFBP VFBPH H H PBGP WBGPP WBGPN VBGP
Pin 50 minimum voltage at which blanking is applied to R, G, B output Pin 50 minimum voltage in which AFC2 operates DC measurement curve slant near f = 15.75 kHz Delay from H sync. rise for both PAL/ NTSC
0.4 1.5 30 1.4 0.2 3.4 2.5
0.75 1.9 37 1.9 0.4 4.0 3.0 4.7 2.4 2.4 1.41 1.11
1.1 2.3 44 2.4 0.6 4.6 3.5 4.9 2.7 2.7 1.51 1.21 19 5.0
V V A/s Hz/mV s s s V V V ms ms s V
PAL burst gate pulse width *8 NTSC burst gate pulse width
*8
Burst gate pulse output voltage
Pin 62 DC voltage during BGP period Pin62 DC voltage during H blanking pulse period Pin62 DC voltage during V blanking pulse period Pulse width at f = 15.625 kHz Pulse width at f = 15.73 kHz Time from H-out rise to FBP center
4.5 2.1 2.1 1.31 1.01 12 2.5
H blanking pulse output voltage VHBLK V blanking pulse output voltage VVBLK PAL V blanking pulse width NTSC V blanking pulse width FBP allowable range
*9
WVP WVN TFBP VAFBP
FBP maximum allowable input voltage I2C interface Bus free before start Start condition set-up time Start condition hold time Low period SCL, SDA High period SCL Rise time SCL, SDA Fall time SCL, SDA Data set-up time (write) Data hold time (write) Acknowledge set-up time Acknowledge hold time Stop condition set-up time
tBUF tSU, STA tHD, STA tLOW tHIGH tr tf tSU, DAT tHD, DAT tSU, ACK tHD, ACK tSU, STO
4.0 4.0 4.0 4.0 4.0 0.25 0 0 4.0

1.0 0.35 3.5
s s s s s s s s s s s s
Note) *1 to *9: Refer to "Explanation of test methods".
14
ICs for TV
s Electrical Characteristics at Ta = 25C (continued)
* Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
AN5095K
Parameter DAC 3-bit, 6-bit, 7-bit DAC DNLE 8-bit DAC DNLE 8-bit DAC DNLE (80) AFT DAC overlap
Symbol
Conditions 1LSB = {data (max.) - data (00)} /7, 63, 127 1LSB = {data (FF) - data (00)} /255 (7F 80 excluded) LSB = {data (FF) - data (00)} /255 (7F 80) 8-bit of AFT double-stage changeover overlap
Min
Typ
Max
Unit
L3,6,7 L8 L8-80 Step
0.1 0.1 0.1 27
1.0 1.0 1.0 32
1.9 1.9 2.9 37
LSB/ Step LSB/ Step LSB/ Step Step
* Explanation of test methods *1: RF AGC delay point adjusting range: VRFdp
[dB] VIF input level
110 100 80 49
00 3F
In the case of VIF gain reduction curve (figure 1), if the RF AGC delay point adjustment DAC (0 A) goes 00 to 3F, the internal comparison voltage changes by V, and the delay point adjustment range is determined.
V [V] IF AGC terminal level
Figure 1. Gain reduction curve *2: AFT discrimination sensitivity: AFT Adjust DAC (0C-D7) and DAC (09) so that the AFT output voltage (V30) becomes approx. 4.5 V when fP = 38.9 MHz. Measure V30 when fP = 38.9 MHz 25 kHz. *3: Refer to "s Technical Information 4. 7) PAL/NTSC, SECAM interface". *4: Black noise detection level: VBN Black noise clamp level: VBNC
VBNC
VP VBN
Figure 2. Black noise rejection characteristic
*5: Inter modulation: IM Apply the signal of fP = 38.9 MHz, 90 dB and fix the voltage of pin 37 (IF AGC) under that condition. fP = 38.9 MHz, 82 dB Input those 3 signals and measure 1.57 MHz component of the fP = 38.9 MHz - 4.43 MHz, 80 dB detection output. fP = 38.9 MHz - 6.0 MHz, 70 dB vieo component [rms] IM = 20Log V1.57 MHz [rms] 15
AN5095K
s Electrical Characteristics at Ta = 25C (continued)
* Explanation of test methods (continued) *6: Black level extension: VBL
ICs for TV
Y output
VBLS VBL1 VBL3
Pedestal level VBL2 Y output when operation is off (Y input)
Figure 3. Black level expansion characteristics
In the black level extension characteristics (figure 3), when the voltage of pin 9 (black level detection filter) is VCC1 = 9 V, the operation of the black level extension circuit is turned off and the characteristic becomes as shown by the line . Also, if the voltage of pin 9 is set at 3 V, the black level extension forcibly comes to start and the characteristic becomes as shown by the line . When pin 9 is set by only R, C filter, the black level extension characteristic as shown by the line can be obtained. VBL3 shows an output level difference between the black extension is off and the normal operation when the video input level is constant in 20 IRE. VBLS is a point where the black extension comes to start and can be adjusted by the DC voltage of pin 48 (CIN). V48 Start point 2.5 V 52 IRE 4.5 V 42 IRE 6.5 V 32 IRE
*7: (C-Y)/Y ratio: RC/Y C-Y is the voltage from 0 level to the peak of B-out when color is typ. (00 = 20) and contrast is typ. (03 = 20). Y is the voltage from the pedestal of contrast at typ. to 100 IRE white level. *8: Burst gate pulse
WBGP PBGP Pin 46 Sync. input BGP (4 s) Pin 62 SCP output
H-sync.
As shown in figure 4, the position of the burst gate pulse is the period from the rise time of the H-sync. signal of pin 46 to the rise time of BGP.
Figure 4. Burst gate pulse
*9: FBP allowable range : tFBP
tFBP
Pin 56 Hor. pulse output
Figure 5 shows the relationship between Hor. pulse and FBP. The phase delay from Hor. pulse to FBP differs from set to set. This IC has an adjusting function for the screen center position. The phase range in which this function normally operate is tFBP.
Pin 50 FBP input Figure 5. FBP allowable range
16
ICs for TV
s Terminal Equivalent Circuits
Pin No. 1 2 3
C
AN5095K
Equivalent circuit
9V (VCC1) Pin 1, 2, 3 300 300 0.01 F
Description
voltage
Pin 1; Primary color signal clamp pin (R) DC Pin 2; Primary color signal clamp pin (G) approx. 7 V Pin 3; Primary color signal clamp pin (B): For the clamp pulse, the internal clamp pulse (BGP) is used.
BGP 150 A
Brightness control
5V (VCC3)
4
3.3 V 1V
0.47 F
Killer det. circuit
BGP 9V 2.8 V
100 A
5
1.0 M
4 137 270 k 2.5 V
Killer filter pin: DC Filter pin of killer detection circuit (operates approx. 3.3 V for BGP period). Killer turns on (without color output) at a voltage of 2.8 V or lower.
Microcomputer VCC (5 V) 33 k To microcomputer 0.47 F 5 175 Floating resistance
40 A 10 k
On
Killer, 50 Hz/60 Hz, SECAM det. output pin: DC Selective output by SW (I2C bus). Low level The load resistance 33 k should be connected 0.2 V to microcomputer VCC . High livel 5V
Off
6
5V (VCC3) 3.3 V
2.2 F
1V
40 k
0.047 F
APC det. circuit
6 SW 2.5 V R 7.5 k
APC filter pin: DC Filter pin of APC detection circuit (operates approx. 2.5 V for BGP period). The detection sensitivity becomes high when the external resistance is high, (tend to be pulled-in easily. tend to be influenced by noise).
curve
BGP
max. 1 mA VCO circuit 270
fC
V6
Stop APC circuit by short-circuiting 40 k at SECAM. 17
AN5095K
s Terminal Equivalent Circuits (continued)
Pin No. 7 8
DC 2.7 V 4.43 MHz 7 C7 12 pF DC 2.7 V 3.58 MHz 8 C8 15 pF
ICs for TV
Equivalent circuit
Description Pin 7; Chroma. oscillation pin (4.43 MHz) Pin 8; Chroma. oscillation pin (3.58 MHz): Either one of the oscillations of 4.43 MHz or 3.58 MHz is performed by chroma. oscillation pin. Frequency changeover is carried out by 08-D7 bit of I2C bus. When 08-D7 = 0; IP1 , IP2 turn on, and 4.43 MHz oscillates When 08-D7 = 0; IN1, IN2 turn on and 3.58 MHz oscillates The pattern from pin to oscillator should be as short as possible.
voltage AC f = fC approx. 0.7 V[p-p]
IP2 100 A
IP1 500 A
IN2 100 100 A A
IN1 500 A
9
-Y
9V (VCC1) 80 A 75 k
5.1 V 9 100 A R 180 k Black expansion circuit 4.7 F
10
50 A
10 k
10 k
Black level detection pin DC approx. 5.1 V Blanking off SW pin: Black level detection filter pin for black 5V extension circuit. (VCC3) Excluding the blanking period, holds the 80 most black Y level. k The sensitivity that the black extension (area judged as black) comes work is To blanking variable by means of external R. When R circuit is large, it responds to a small area. Apply VCC (9 V) to pin 9 when stopping the black extension circuit. Blanking is turned off when pin 9 is GND (black extension is also off). YS input pin: Fast-blanking pulse input pin for external analog R, G, B. On at a voltage over 1 V. Off at a voltage under 0.4 V. AC (pulse)
9V (VCC1) To R, G, B output circuit
From microcomputer 2.7 k 10 30 k 100 A
0.7 V
18
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 11 12 13
Pin 11 12 13 To color circuit BGP
AN5095K
Equivalent circuit
9V (VCC1) 100 A
Description Pin11; External R input pin Pin12; External G input pin Pin13; External B input pin: The output will change linearly depending on the input level.
voltage AC
200 A
14
VCC1 (9 V typ.): Output block of VIF, SIF circuit. AV SW circuit. Video circuit. RGB circuit.
9V (VCC1)
DC 9V
15 16 17
C-out
100 A
100 50
Pin 15 16 17
Pin15; R-out pin Pin16; G-out pin Pin17; B-out pin: BLK level approx. 0.9 V. Black (pedestal) level approx. 2.2 V. Blanking can be released by setting pin 9 (black level detection pin) at 0 V. Horizontal synch. detection pin: The phase of horizontal sync. signal and horizontal output pulse is detected and outputted. Pin 18 becomes low if out of synchronization. Color control becomes minimum and chroma signal disappears in asynchronous state. Pay attention to impedance when the voltage of pin 18 is utilized for microcomputer. (500 k or higher ZO is required)
AC
500 A
18
6.3 V (VCC2) 10 k 2.8 V 800 A I1 800 A I2 50 A 12 k 12 k To chroma circuit 5V (VCC3)
DC When synchronous approx. 6 V When asynchronous approx. 0.3 V
18 ZO 0.022 F
Pin56 H-out Pin46 H/V sync. in
10 k
1 M
H Sync. period When pin 56 is high: I1 on When pin 56 is low: I2 on
19
AN5095K
s Terminal Equivalent Circuits (continued)
Pin No. 19 Equivalent circuit Description GND: R, G, B circuit. DAC, I2C circuit.
9V (VCC1) 5.9 V 60 k 60 k 6.9 k 2.3 V Contrast control 2.3 V 1 V 100 A 100 A 7.1 k 7.1 k 6.9 k 100 A 6.9 k 20 4.7 F To contrast circuit 2.1 V 3.5 V
ICs for TV
voltage
20
ACL pin: If DC voltage of pin 20 is decreased from the outside, the contrast is turned down. Service SW.
Note) Since pin 20 also serves as the service SW when used as ALC, design the set so as not to allow V20 < 0.9 V.
DC approx. 3 V
21
100 k Data 21 From microcomputer ACK 30 k 1 k 50 A
5V (VCC3) 100 k 1.7 V
I2C bus data input pin
AC (pulse)
To logic circuit 30 k
22
100 k Clock 1 k 22 From microcomputer 50 A
5V (VCC3) 100 k 1.7 V
I2C clock input pin
AC (pulse)
30 k
To logic circuit 30 k
23
VCC3-1 (5 V typ.): For VIF and SIF circuitr.
DC 5V
20
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 24 25
3.5 V 27 k 25 SAW 24 1.2 1.2 k k
AN5095K
Equivalent circuit
5V (VCC3)
Description Pin24; VIF input pin-1 Pin25; VIF input pin-2: Balanced input by VIF amp. input.
voltage AC f = fP DC level approx. 2.7 V
150 A 150 A
26 27
GND: For VIF and SIF circuit.
5V (VCC3)
DC DC
RF AGC output pin: Open collector output and usable at any bias value (12 V max.).
To tuner 27
1F AGC bias RF AGC control bias 40 k
28
9V (VCC1) 270 28
Audio output pin
AC 0 kHz to 20 kHz
100 A 400 A
29
Detection output 120 k PAL 60 k NTSC 29 1200 pF 1.7 k
9V (VCC1)
100 A
De-emphasis pin: De-emphasis filter pin for sound detection signal. External C for PAL/NTSC is the same (internal impedance changes). PAL: 12 k//60 k x 1 200 pF = 48 s NTSC: 60 k x 1 200 pF = 72 s
AC 0 kHz to 20 kHz
21
AN5095K
s Terminal Equivalent Circuits (continued)
Pin No. 30
1.1 k 1.1 k 9V
ICs for TV
Equivalent circuit
9V (VCC1)
Description AFT output pin: Offset of center voltage is adjusted by using bus. When AFT defeat SW is turned on (09 = 00), V30 becomes a value determined by external resistor-divider. of AFT is variable by impedance of external resistor.
voltage DC
30
To tuner
1.1 k
40 k 1.1 k 350 max.
31
50 A To video SW 3.4 V 30 k 50 k 31
9V (VCC1) Ext. video
External video input signal pin: AC External video signal input pin and DC cut 1 V[p-p] input. (compost) Typical 1 V[p-p].
10 F
100 A
DC approx. 2.0 V Decoupling pin: S-curve inside the IC is broad-band. However, DC feedback should be applied so that DC voltage of output signal becomes constant. DC level (4.5 V typ.). fS high: V32 low DC
32
10 k
9V (VCC1)
4.5 V typ. 3 k 3 k
1.7 k 32 1.7 k 10 F
20 k 100 A 13 A 9V (VCC1) 33 10 pF 30 k SIF in 1.8 k 5 V to 7 V 30 k 200 A 9V 100 A 100 A To SIF limitter amp. 4.4 V
33
SIF signal input pin: Used in common as DC input pin for sharpness control. DC bias is applied from outside (for sharpness control DC: 5 V to 7 V).
AC+DC AC f = fS
Sharpness contorol
22
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 34
53 k 1.24 V 34 1 F 56 A
AN5095K
Equivalent circuit
5V (VCC3) To SIF PLL
Description SIF internal power supply stabilization filter pin
voltage DC 1.24 V
35
9V (VCC1) 100 A SIF in Pin 35, 36 40 k 30 k 30 k 9V 200 A 100 A To SIF limitter amp. 3.7 V
SIF signal input pin: Input pin for SIF2 and internally biased.
AC+DC AC f = fS DC 3.0 V
36
1.8 k
SIF signal input pin: Input pin for SIF1 and internally biased.
37
5V (VCC3)
To IF amp. 30 A 37 0.47 F
IF AGC filter pin: DC IF AGC filter pin. The current obtained from approx. 2 V peak AGC circuit is smoothed by an external capacitor. When C goes smaller, the respons charaeteristic becomes faster but the sag tends to appear easily.
38
50 A To video SW 3.0 V 30 k Pin 38, 40
9V (VCC1) Int. video
Internal video input pin 1: Input pin for the signal detected by VIF circuit (internal video signal). DC cut input. Typical 1 V[p-p]
AC 1 V[p-p] (compost)
10 F 680 k
DC level approx. 1.6 V
23
AN5095K
s Terminal Equivalent Circuits (continued)
Pin No. 39 Equivalent circuit
9V (VCC1) VCO (4 MHz to 7 MHz) P.C. 8.4 k 800 A 13 k 2 pF 72 A 5.6 k 39 1 000 pF 7.5 k To audio SW
ICs for TV
Description SIF APC filter pin: Filter pin for SIF APC circuit.
voltage DC
200 A 9V (VCC1) Int. video 30 k Pin 38, 40 10 F 680 k
40
50 A To video SW 3.0 V
Internal video input pin 2: Input pin for the signal detected by VIF circuit (internal video signal). DC cut input. Typical 1 V[p-p].
AC 1 V[p-p] (compost)
DC level approx. 1.6 V VIF detection output pin: Adjust at 2 V[p-p] by I2C bus (upper 4-bit of 0 A is used).
Note) At AV mode, VIF detection signal output is not given.
41
75 A 41
9V (VCC1)
AC 2 V[p-p]
42
50 A 1 SW 0
5V (VCC3)
500 20 k 42 150 3.25 V 75 A 0.47 F
APC1 filter pin: Filter pin for APC1 circuit of VIF. Lock detection circuit of VCO is built in the IC inside and the time constant of APC filter is changed over. When locked SW: 0 When not locked SW: 1
DC approx. 2.5 V
To VCO 25 A
24
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 43 Equivalent circuit
5V (VCC3)
AN5095K
Description VIF oscillation pin: Depending on VIF frequency, change oscillation coil. The oscillation frequency is 1/2 of fP .
voltage AC f = fP /2 approx. 0.7 V[p-p] DC level approx. 3.9 V
100 300 43
800 A 400 A
100 A
44
50 A 44 9V (VCC1)
Video output pin: This pin outputs int.video 1, int. video 2 or ext. video signal selected by AV SW.
AC 2 V[p-p]
DC level approx. 4.5 V
400 A
45
47 k 4.3 V 45 10 A 1.8 k 43 k
9V (VCC1) 50 A
Video input pin: Input pin for video signal (composite video also available). Typical input 0.6 V[p-p]. Sync. top is clamped at 3.5 V. The video signal should be inputted with low impedance.
AC 0.6 V[p-p]
46
2 V[p-p] 16 k
5V (VCC3) 16 k To H-sync. sep. V-sync. sep. 1.3 V
Vertical and horizontal sync. separation input pin: Sync. top is clamped at 1.3 V.
AC 2 V[p-p]
RH 0.1 F 270
46
CH 1 200 pF 20 A
47
VCC3-2 (5 V typ.) For chroma jungle circuit.
DC 5V
25
AN5095K
s Terminal Equivalent Circuits (continued)
Pin No. 48
Chroma signal 1 000 pF 9V 10 k 10 k 48 12.5 pF 15 k 2.5 V To chroma amp. 50 A 9V (VCC1)
ICs for TV
Equivalent circuit
5V (VCC3)
Description Chroma signal input pin Black extension start point adjusting pin: black extension start point is adjusted by DC voltage applied from the outside.
voltage AC+DC burst DC 4.5 V typ.
Pin 48 is chroma signal input pin, and the 150 mV[p-p] typ.
To black level expansion 100 A 25 A
49 50
100 A 50 A 100 A 5V (VCC3) 50 A
GND: For video chroma jungle circuit. FBP input pin: FBP input pin for horizontal blanking and AFC circuit. Threshold level H-BLK: 0.7 V AFC: 1.9 V It becomes all blanking when DC 1.3 V is applied from the outside.
DC 0V AC FBP
1.9 V 24 k 0.7 V
To AFC 60 k To H-BLK 40 k 50 40 k
50 A
51
I51 15 mA typ. 47 F VCC2 51
Horizontal stabilized power supply pin: Stabilized power supply for starting up the horizontal circuit that has a zener circuit inside.
To hor. OSC
DC 6.3 V
V51 6.3V
I51
52
2 k 2 k 1.9 V
6.3 V (VCC2) To hor. out
V52
AFC2 detecter
I
From DAC 52 (hor. position)
3.3 V
1 k
1 k
0.022 F 50 A
500 A max.
Horizontal AFC2 filter pin: Comparing the phase of FBP and that of inside pulse of the IC, charge to and discharge from the capacitor connected to pin 52 are done. Performed by charging and discharging in DC current by the screen center position adjusting DAC. V52 changes depending on the time from H-out to FBP, and the slice level of internal sawtooth waveform changes.
DC 1.5 V to 3.5 V
26
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 53
4.3 V
AFC1 detecter
AN5095K
Equivalent circuit
6.3 V (VCC2)
Description Horizontal AFC1 filter pin: Comparing the phase of horizontal sync. signal and that of inside pulse of the IC, charge to and discharge from the capacitor connected to pin 53 are done. R1, R2, C1, and C2 are lag-lead filter for AFC1. Horizontal curve fH
voltage DC 4.3 V typ.
R1 27 k 1.5 V 53
27 k
Hor. sync.
22 F C2 820 R2
0.033 F C1 200 A
Hor. OSC
1 000 A
V53
6.3 V (VCC2)
54
22 k 300 54 100 A 220 pF 200 A 10 k 10 k 80 A
Horizontal oscillation pin: Oscillate at 32 x fH 503 kHz by means of ceramic oscillator. Horizontal and vertical pulse are generated by means of count down circuit in the IC.
(
AC f = 32 fH approx. 503 kHz
)
55
4.3 V 20 k 20 k 40 k 3V
6.3 V (VCC2)
55
To count down 20 k
Overvoltage protection input pin: Input pin for the protect circuit against X-ray due to overvoltage. Shut-down is started by internal logic circuit when H-out pulse is low. (Prevent the horizontal drive Tr destruction.) Horizontal pulse output pin: Duty cycle is approx. 36%.
DC normally 0V
56
4.3 V 19 k 50 10 k 40 k
6.3 V (VCC2)
AC pulse
56 2.8 V 0V Hor. Out
27
AN5095K
s Terminal Equivalent Circuits (continued)
Pin No. 57
4.3 V 16 k 4 k 270 57 200 R2 220 R1 330 k C1 0.33 F To ver. count down 50 k
ICs for TV
Equivalent circuit
5V (VCC3) 3 k
Description Vertical sync. signal clamp pin: Peak clamp pin for separating vertical sync. signal. Although the integral amount of vertical sync. signal itself has been determined by the internal time constant, the trigger application timing is determined by selecting external constant R1, C1. R1 must be used at higher than 200 k. R2 is resistor for emitter current restriction. Vertical pulse output pin: Negative polarity, pulse width of 10H.
voltage AC f = fV
58
5V 50 k (VCC3) 58 4.3 V 43 k 0V
AC pulse
59
fC 56.2 k 12 k 50 A
12 k
9V (VCC1)
13.7 k 61.5 k 50 k
59 To SECAM IC
200 A 100 A SECAM SECAM detecter SECAM
SECAM interface pin: AC+DC Input and output pin for interfacing with AC SECAM IC. 250 mV[p-p] It becomes the SECAM mode when the or 0 mV[p-p] current sink from pin 59 is 100 A or more. DC 4.4 V At SECAM or 1.1 V DC 4.4 V + AC 250 mV[p-p] At non-SECAM DC 1.1 V + AC 250 mV[p-p]: 4.43 MHz or 0 mV[p-p]: 3.58 MHz
60 61
100 A
100 A
100 A
5V (VCC3) -(B-Y) 60 61 -(R-Y) To 1HDL
Pin60; -(B-Y) output pin Pin61; -(R-Y) output pin: The output circuit turns off at SECAM and becomes a high impedance state. Outputs to 1HDL.
AC -(B-Y)
-(R-Y)
SECAM 0V SECAM
1.5 k 2.5 k
1.5 k
DC level approx. 2.1 V
28
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 62
37 k V-BLK 42 k 63 k 44 k H-BLK BGP
9V (VCC1) 100 A
AN5095K
Equivalent circuit
15 k 5V (VCC3)
Description Sand-castle pulse output pin: The sand-castle pulse is outputted to 1HDL and SECAM IC.
voltage AC pulse
62
4.7 V 2.4 V
63 64
Pin 63, 64 From 1HDL CCP To color circuit
Pin63; -(B-Y) input pin Pin64; -(R-Y) input pin: The color difference signal outputted from 1HDL is inputted. The pedestal level is clamped at 4 V by means of clamp circuit.
AC -(B-Y)
-(R-Y)
200 A
DC level 4V
s Usage Notes
1. The following terminals are not strongly resistant to surge latch-up. The precautions should be observed when using the IC. 1) Serge The + side breakdown voltage of pin 22 and pin 23 is approx. 190 V if the surge source capacitance is 200 pF. The + side breakdown voltage of pin 45 is approx. 160 V if the surge source capacitance is 200 pF. Therefore, do not apply a surge stronger than that. 2) Latch-up For pin 18, pin 21, pin 22, pin 51, pin 54, pin 55 and pin 56, the latch-up occurs by the + side surge of approx. 150 V (surge source capacitance 200 pF). Therefore, do not apply a surge stronger than each voltage indicated for each pin.
Note) The stronger surge common to the above 1) and 2) means that the establishment of either one of the following two cases; the surge source capacitance is larger than the indicated value or the surge voltage is higher than the indicated value.
29
AN5095K
s Usage Notes (continued)
2. The protection diode of each Pin is as shown in the following table;
ICs for TV
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 With ( q ) or Without ( x ) Surge diode VCC GND
q q q q q q q q q q q q q q q q q q q q q q q q q q
x x
q q
q q
q q
q q
x x
q q
xxx xxx
q q
q q
x x
VCC node being connected
1113333311111
1112
1
33
Pin 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 With ( q ) or Without ( x ) Surge diode VCC GND
q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q
x x
q q
x x
q q
x x
q q
VCC node being connected
11111113113111133311
3
3
VCC VCC
2
Pin 53 54 55 56 57 58 59 60 61 62 63 64 With ( q ) or Without ( x ) Surge diode VCC GND
q q q q q q q q q q q q q q q q q q q q q q q q
VCC node 1 VCC1 (9 V system) 2 VCC2 (6.5 V system) 3 VCC3 (5 V system)
side diode
VCC node being connected
222233133311
GND
side diode
GND
s Technical Information
* Explanation of each block 1. VIF 1) Adapting the inter carrier PLL coherent detection method. 2) The VCO of VIF is controlled by I2C bus (7-bit): Oscillation at 1/2 of the fP frequency. (2 times multiplier circuit is inside.) Built-in double APC circuit of frequency and phase. 3) AFT without coil: It is applicable to both VS and FS tuners by amplifying the error voltage of APC and making S-curve to obtain AFT output. The DC offset is controlled by I2C bus (9-bit). The AFT defeat is also possible. 4) Since the VCO oscillates at 1/2 frequency, a high-frequency disturbance such as tweet is reduced. 5) The video detection output is 2.0 V[p-p] typical: The level adjustment is carried out by I2C bus . 6) The built-in lock detection circuit realizes a stable pulling by the changeover of time constant for APC. 7) The delay point of RF AGC is adjusted by I2C bus (6-bit). 2. SIF 1) The SIF detection uses PLL coherent detection method. 2) 4 frequencies are changed over for use as the VCO oscillation frequency. At NTSC; 4.5 MHz At PAL; 5.0 MHz, 5.5 MHz, 6.5 MHz 3) It is possible for the SIF detection output to deal with the difference in deviation of PAL/NTSC by changing over an amplifier of +6 dB. 4) Built-in video/SIF SW. Video SW; 2 systems (with 6 dB amp.) SIFSW; 3 systems
30
ICs for TV
s Technical Information (continued)
* Explanation of each block (continued) 3. Video 1) The delay line aperture control (contours emphasis type) is used for sharpness control. The circuit as well as the black extension circuit realizes a high picture quality. 2) Built-in pedestal clamp filter. 3) Service SW: (Y contrast min., vertical output stop).
AN5095K
4. Chroma 1) The circuit realizes an adjustment free condition by using base band 1HDL (externally attached). 2) Incorporation of ACC filter reduces the number of external components. 3) It is possible to support the other systems by the mode changeover I2C bus (1) PAL/NTSC, (2) 4.43 MHz/3.58 MHz, (3) Forced PN/ForcedSECAM. 4) Equipped with the killer output terminal for system discrimination by microcomputer. (When killer is on 0 V, killer is off 5 V) 5) The color difference output terminal becomes a high impedance state at SECAM. 6) Since the circuit is provided with the color difference input terminal, the features of ICs such as the AN5244 (IC for color signal compensation) can be connected. 7) PAL/NTSC, SECAM interface (pin 59) Mode PAL/NTSC DAC(3.58 MHz/4.43 MHz) Pin59 output 3.58 MHz 4.43 MHz SECAM 3.58 MHz 4.43 MHz Approx. 1.3 V Approx. 1.3 V Approx. 4.6 V Approx. 4.6 V fC 3.58 MHz 4.43 MHz 4.43 MHz 4.43 MHz AC level x 250 mV[p-p] 250 mV[p-p] 250mV[p-p] Output for V-blank period only * CW output
Note) *: AC component of 4.43 MHz is outputted in the vertical sweep period only.
V-sync.
Input
Approx. DC 4.6 V
250 mV[p-p] Pin 59 V-blank (R, G, B out)
5. RGB 1) It supports not only the OSD but also the teletext signal in an analog input system. (The output level is interlocked with the contrast of TV signal side.) 2) The white balance (drive, cut-off) adjustment is performed by I2C bus. 6. Jungle 1) The horizontal circuit uses the count down method by 32 fH ceramic oscillator. The AFC circuit uses double method. 2) By the adaption of trigger method count down circuit, the vertical circuit can obtain a stable vertical synchronization without adjustment at all times. The output is pulse signal, so that there is no degradation of interface due to the influence of pattern layout.
31
AN5095K
s Technical Information (continued)
* Explanation of each block (continued)
ICs for TV
6. Jungle (continued) 3) Built-in frequency discrimination circuit: The circuit outputs the judgment results of 50 Hz/60 Hz in accordance with the frequency of the vertical synchronizing signal. (60 Hz high) Input frequency Judgement Output voltage Hold 45 50 Hz (Low) 55 60 Hz (High) 65 Hold
4) The output holds the previous state when the input frequency is 45 Hz or less and 65 Hz or more, and the output changes for the first time when judged as 50 Hz or 60 Hz for 3 consecutive vertical periods. 5) The horizontal detection circuit and X-ray protection circuit (shut-down method) are built in. 6) The screen center position is adjustable by the I2C bus. (1.6 s) 7) For the blue-back in a weak electric field, the stable screen image is held by the vertical trigger off mode ( I2C bus). 7. I2C bus 1) Incorporating 14 DAC controls and 12 SWs for eliminating the need for the adjustment of set mechanism. 2) Provided with automatic increment function. * Sub address 0 *: Automatic increment mode. (When data are sent in regular succession, sub address changes successively and data are inputted.) * Sub address 8 *: (When data are sent in regular succession, data are inputted with the same sub address.) 3) I2C Bus Protocol * Slave address: 10 001 010 (8AH) * Slave address format S Slave address 0 A Sub address A Data byte A P
Start condition
Write
Acknowledge bit
Stop condition
4) Sub address byte and data byte format The description in ( ) shows the initial state.
Sub address 00 (21H) 01 (21H) 02 (41H) 03 (21H) 04 (81H) 05 (81H) 06 (81H) D7 P/N (0 P) Ver. auto (0 auto) Ver. OSC (0 50) SIF SW D6 PN/S (0 PN) Ver. TRG (0 normal) D5 Data byte D4 D3 Color Tint Brightness Video SW Contrast Cut off R Cut off G Cut off B D2 D1 D0
32
ICs for TV
s Technical Information (continued)
* Explanation of each block (continued) 7. I2C bus (continued) 4) Sub address byte and data byte format (continued) The description in ( ) shows the initial state. Sub address 07 (41H) 08 (41H) 09 (01H) 0A (21H) 0B (45H) 0C (C1H) 50 Hz/60 Hz killer out SW SIF/ext. SW AFT offset SW SECAM det. SW Video adjust D7 SIF VCO SW1 Chroma VCO (0 4.43) D6 D5 Data byte D4 D3 Drive R Drive B AFT offset RF AGC delay SIF VCO SW2 VIF VCO D2 D1
AN5095K
D0
H center
5) Contents of I2C bus control (1) The control information is in the direction that the output increases when the datum increases. (Example: Contrast 00 contrast min. , 3F max. , brightness 00 pedestal level low, 7F high) (2) Supplement of other control a. 00: Color When data are 00, the color becomes off since the chroma output is decreased completely . b. 01: Tint Data 00 Skin color tends to become reddish, 3F skin color tends to become greenish. c. 04, 05, 06: Cut off R, G, B 8-bit DAC d. 07, 08: Driver R, B 7-bit DAC e. 09: AFT offset adjustment The DC offset of S-curve of AFT output is corrected. Data 01 S-curve falls (DC voltage of center frequency drops). Data FF S-curve rises. It becomes AFT defeat mode when data 00, the voltage of AFT out (pin 30) becomes the value in accordance with the external resistor. AFT changes over 8-bit DAC into 2 stages for variable range and improvement of precision for per 1-bit. Example: In the case of AFT
Output
Overlap approx. 1/8
0A: 00 0C-D7: 0
FF 0, 1
00
Data FF 1 33
AN5095K
s Technical Information (continued)
* Explanation of each block (continued)
ICs for TV
7. I2C bus (continued) 5) Contents of I2C bus control (continued) (2) Supplement of other control (continued) f. 0A: RF AGC delay point adjustment The same operation as when bias is applied from outside conventionally. Data 00 DC-applied bias drops delay point rises Data 3F DC-applied bias drops delay point down g. 0B: Video adjustment Data 0* detection output min. 7* max. to be used for correcting the dispersion of detection output inside the IC. h. 0B: Hor. screen image position Data *0 screen image goes to the left 7 * screen image shifts to the right. i. 0C: VCO control Fine control for the oscillation frequency of VCO (1/2 frequency of fP) of VIF. 8. Supplementary explanation of SW operation Data-bit 00-D7 SW contents PAL/NTSC mode SW (0 PAL) (1 NTSC) 1) 2) 3) 4) Concrete contents BGP width changeover (PAL: Wide) CW changeover to killer (PAL: 90 deg./270 deg.) Tint operation changeover (PAL: Tint off) Ident operation changeover (PAL: With operation)
00-D6
PAL, NTSC/SECAM mode SW 1) Demodulation output mode changeover. (1 forced SECAM) The color difference output terminal becomes high (0 normal discrimination mode) impedance at forced SECAM. Ver. auto SW (0 auto changeover) (1 manual changeover) 1) Vertical frequency discrimination circuit changeover. Auto changeover: Automatic discrimination mode by internal counter. Manual changeover: Forcibly changeover 50 Hz/60 Hz by 02-D7 data. 1) Vertical trigger input inhibit SW. 1 trigger input-off is the mode to protect from the vertical dancing caused by noise at blue-back . 1) Vertical frequency changeover SW. Valid only when 01-D7 is 1.
01-D7
01-D6
Ver. TRG stop SW (0 normal) (1 trigger off) Ver. OSC SW (0 50 Hz) (1 60 Hz) 03-D7 0 0 1 1 0B-D7 0 1 0 1
02-D7
03-D7 0B-D7
SIF, external AV input changeover switch Output signal SIF1 (int.) SIF2 (int.) SIF3 (int.) Ext. (video) Int. is set at SIF1 Power on time
34
ICs for TV
s Technical Information (continued)
* Explanation of each block (continued) 8. Supplementary explanation of SW operation (continued) Data-bit 03-D6 SW contents Video input changeover switch 03-D6 0 1 08-D7 Chroma VCO SW (0 4.43 MHz) (1 3.58 MHz) 0A-D6 0 0 1
Mode
AN5095K
Concrete contents Input signal Video1 Video2 1) Chroma oscillation circuit changeover. Power on time
0A-D7 0A-D6
50 Hz/60 Hz, killer, SECAM det. out switch 0A-D7 0 1 0 Output signal 50 Hz/60 Hz out Killer out SECAM det. out Killer out Off (color) On (B/W) SECAM det. out SECAM No SECAM Power on time
Output
50 Hz/60 Hz out 60 Hz 50 Hz
H (5 V) L (0 V) 07-D7 0B-D3
SIF VCO free-running frequency, de-emphasis Detection output gain changeover switch 07-D7 0B-D3 De-emphasis/gain Oscillation frequency of VCO SIF input terminal 1 1 0 0 0 1 0 1 NTSC PAL PAL PAL 4.5 MHz (power on time) 5.5 MHz 6.0 MHz 6.5 MHz
0C-D7
AFT offset SW (0 without offset) (1 with offset)
1) For AFT 2-stage changeover. (Power on preset: AFT offset SW 1) 2) AFT defeat. Defeat comes ettective only when 0C-D7 = 0, DAC(09) = 00.
35
AN5095K
s Application Circuit Example
100 F
AN78M09
ICs for TV
VCC3=5 V 21
9
0.01 F
8 7 6
SECAM
47 F 1.8 k
VCC1 = 9 V AN78M05
10 11 12
Video Video out in
0.22 F 0.1 F
0.1 F 82 H 82 H 33 pF
33 pF
9 10
-(R-Y) -(B-Y)
8
7 0.047 F 6 5 4 3
0.1 F
5 4 3
0.022 F 47 F
51
0.022 F
R G B Clamp filter
1 2 3 4 5 6 7 8 9 10 11
64
In
0.1 F 0.1 F
11 12 13
820 0.047 F
13 14 15 16
0.022 F 0.022 F 0.47 F
63
SCP
47 F
1 M
62 61 60 59 58 57 56 55
2 1
(8 V)
54321
MN3868(1H DL)
Killer out 50 Hz/60 Hz out SECAM det. out
0.01 F
14
0.1 F -(R-Y) -(B-Y) out out
Killer
0.01 F 15
2 1
5V
33 k 15 k 15 k
1234567 VCC1 (9 V)
16
2.2 F APC 0.047 F 4.43 MHz 12 pF 3.58 MHz 15 pF B L 4.7 F det. 180 k YS 1 M 0.47 F 0.47 F 0.47 F R
0.47 F
0.1 F SECAM interface
U-COM
V-out 220 2.2 F
Ver. clamp H-out
8.2 H 33 pF
123 2.2 k 10 k
680 k 10 k
X-ray protect. HOSC
47 pF
54 53 52
220 pF
10 kB
12
G
10 F 820
AFC1 0.033 F AFC2
1 k
13
47 F B
0.022 F
VCC2
Trap&DL (340 nsec 35 nsec) 9V
14 15
51 50 49 48
47 F 180
1.8 k
1.5 k 1.5 k 1.5 k R
12345 Hor. lock det.
3.3 k
16
G
FBP in (VCJ) GND 10 k 10 k C in
1.2 k
56 H 30 pF 10 k
1.8 k
3.58 MHz Trap
17
0.022 F 1 M GND (RGB/DAC) B
120 pF
21
18 19 20
ACL
47
(VCJ)
1000 pF
VCC3 5V
47 F
2.7 H 150 pF 10 k
100 pF 4.7 H
3.58/4.43 On
46
10 k 3.6 k
0.1 F 1200 pF
Sync. in
270
1 V[p-p]
2 k
4.7 F 4.7 k
4321 0.01 F
21
SDA
45 44 43 42 41
Y in 10 F
9V
4.7 k 0.01 F 47 F
SAW
22
SCL
1 k 2.2 k
2 V[p-p]
Video out
6.5 H
6.0 H
23
VCC3 (VIF/SIF)
0.39 H
VOSC 0.47 F 150 APC1
24 25 26 27 28
910 1.2 H 7.5 k
910
10 F 910 9V
1200 pF Det. out 680 k
910 910
56
0.01 F GND (VIF/SIF) 6.8 k
21 Audio out
40 39 38 37 36 35
SIF2 in Int. V1 0.47 F SIF1 in
12 H
Int. V2130 k
SIF APC
0.01 F
1 k
Trap 5.5 H
0.01 F
RF AGC 39 k
1000 pF
470
BPF 470 6.5 MHz
470
10 F 1200 pF De-emphasis
680 k AGC 0.01 F 0.01 F
8.2 H
29 30
BPF 5.5 MHz /6.0 MHz
1F BM AFT BL AGC BH BT BU
47F 10F 10F 10F 10F 10F 10F
150 k 150 k AFT
470
31
10 F Decoupling 75
Ext.video 3 Band SW 2 4 SW1 1 +B (12 V) 10 kB
BPF 4.5 MHz
32
34 33
Ext.audio in SIF3 in sharpness
5.1 k 10 kB Sharpness
10 F 0.01 F
470
10 F
470
TU1
36

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